I wrote the code about in given question. Please explainmy code step by step and how does it work. For example "what is themeaning of Q<=Data[3] what does it do ; etc..." Please explainall steps about it. In shortly, explain my code. Name of codeis..... Inputs are... outputs are... this meaning... I hope it'sclear. Thanks

1-) Explain your codes step by step. How it works and what does your code do ? a.) 4-Bit Synchronous Parallel Load Shift Register with Counter and Asynchronous Reset: Write a Verilog code to read an 8-bit message from parallel input (user switches) into a shift-register, and use the shift function together with a counter to determine the number of '1's in the message (Don't use behavioral design instead used flip-flops). (no need for designing the 7-segment LED decoder here, the decoder will be used during the experimental work.) module countones (rst, Data,Clk,load, Q,Ones); input rst; input [7:0] Data; input Clk,load; output reg 13:01 Ones; output reg [7:01: output reg (7:0) mask, temp always@( posedge clk or negedge rst) begin if(!rst) begin Q<=8; Ones<=0; end else if (!clk) begin Q<=0; Ones<=0; end else if(load) begin Q<=Data; Ones<=0; end else if(!load) begin Q<=Data; Ones<=Data[3]; end end endmodule