2.Sketch the complete schematic for a pipeline ADC stage that resolves 1 bitper stage,including sub-ADC and multiplying DAC (MDAC).The stageshould resolve input values from 0 to +VREF,and produce a residue thathas the same range.The MDAC should be based off of the‘flip-around'switched capacitor amplifier discussed earlier this semester.Values of allcapacitors should be given relative to an arbitrary unit capacitance valueC.